1. Field of the Invention
The present invention relates to a phase locked loop (hereinafter, called PLL), and particularly relates to a digital PLL for reproducing the standard clock at a receiving side in a transfer system of the standard clock used for image coding for systems larger than current TV systems such as MPEG 2 (Motion Picture Experts Group 2).
2. Background Art
According to the specification of MPEG of the International Organization for Standardization (ISO), wherein the digital transfer systems of the dynamic image are under investigation, a transmitting side transmits a numerical information corresponding to a count of a transmitting counter by reading the count at random time intervals, while, a PLL at the receiving side reproduces a standard clock synchronized with that of the transmitting side based on numerical information obtained as a difference by comparing between the numerical information at the transmitting side and the count of the standard clock obtained by counting at the receiving side. A digital signal processing-type PLL is known as a circuit for reproducing the standard clock from the second numerical information.
Experimental and simulation results including of a first order-, a second order- and third order- all digital type PLLs are reported in a paper entitled xe2x80x9cResponse of an All Digital Phase-Locked Loopxe2x80x9d by Joseph Garodnick et al. in xe2x80x98IEEE transactions on Communication, vol. COM-22, No. 6, June 1974xe2x80x99.
The operation of this digital signal processing-type DPLL (Digital PLL) will be described hereinafter referring to a block diagram shown in FIG. 7.
An input of a receiving FM wave including noise is turned into X(t) as a wave with a restricted band by passing a band-pass filter BPF having a band width B, and after sampling, X(t) is subsequently turned into a digital signal Xk after conversion into binary codes by an A/D converter. The digital signal Xk generates a phase error signal Ek by inputting the signal with an output Wk of VCO (Voltage Controlled Oscillator) into a multiplier which corresponds to a phase comparator. The phase error signal Ek is turned into a control signal Yk by passing it through a digital filter and determining the output Wk+1 of the new VCO. While, after the control signal Yk is converted into a step-wise signal by a D/A converter as the output of the loop, the control signal is taken out as an analog signal Y(t) by LPF (Low Pass Filter). There are various types of digital filters such as a linear pass type-, a linear plus integral pass type-, and a linear plus integral plus double integral pass type-filters, and these filters are called first order-, second order-, and third order- DPLLs.
In the conventional digital signal processing type PLL, a problem arises that, since the transmitting clock information is processed assuming that the information is sampled at a fixed cycle, jitter suppression characteristics of the system become unstable when PLL is driven by information sampled at random time intervals, which results in deteriorating the transmission quality.
That is, in the digital signal processing type-DPLL, calculation is performed using a fixed differential time, since essential elements such as the primary low pass filter and the integrator are formed by a delay element having a fixed delay time of Ts second. However, when sampling intervals w are random, since scattering of the arrival time of numerical information causes fluctuation of the delay time each time and fluctuation of the time constant of the delay element, the jitter suppression characteristic of the system becomes unstable.
Therefore, it is an object of the present invention to provide a PLL capable of reproducing the standard clock which is fixed in a stable jitter band from the random time information.
The present invention is directed from a point that an equation 1, which represents the time integral,
y=∫f(t)dtxe2x80x83xe2x80x83(1)
can be replaced with an equation 2.
y=xcexa3f(i) xcex94txe2x80x83xe2x80x83(2)
That is, the delay line of the present invention is capable of operating in response to random time information by using xcex94t obtained from a differential time between the present count T(i) and the preceding count T(i-1) as an operator for each constituting elements.
The perfect second order PLL according to the present invention comprises
a receiving counter, which has the same structure with that of a counter at the transmitting side, for counting the received standard clock;
a memory for storing the output of the receiving counter;
a subtractor, which reads the counted value of the counter at the receiving side each time the counted value of the transmitting side is transmitted to the receiving side, for comparing between the counted value transmitted and the counted value of the counter at the receiving side;
a differential time calculator for calculating a differential time between the present counted value and the preceding counted value of the receiving counter at the receiving side;
a first attenuator for attenuating the output gain of the subtractor;
a second attenuator for attenuating the output of the first attenuator;
an integrator for integrating the output of the second attenuator based on the differential time calculated by the differential time calculator;
an adder for adding the output of the first attenuator to the output of the integrator;
a converter for converting the result of the adder into a voltage signal;
a voltage oscillator for converting and receiving said voltage signal of the output of the converter, and converting into a control signal for outputting into the receiving counter.
FIG. 2 shows a third order PLL according to the present invention having a primary low pass filter which receives the output of the subtractor of the second order PLL and the output of the differential time calculator and inputs its output to the first attenuator.
Operations and actions of the present device will be described hereinafter for a case of the primary low pass filter.
FIG. 4 shows a structure of the primary low pass filter, FIG. 5 shows its extended view in the Z plane, and FIG. 6 shows a frequency response characteristic of this circuit.
As shown in FIG. 4, the primary low pass filter can be constructed by an RC circuit. The frequency transfer characteristic Y(jxcfx89) is expressed by,
Y(jxcfx89)=1/(jxcfx89RC+1)xe2x80x83xe2x80x83(3)
that is, on the S plane, the equation in turned into,
Y(S)=1/(S/A+1)xe2x80x83xe2x80x83(4)
where, A is a gain of this system, which is a reciprocal of the time constant 1/RC.
When this transfer characteristics is extended on the Z plane, S is expressed as,
S=(1xe2x88x92Zxe2x88x921)/xcex94txe2x80x83xe2x80x83(5)
Here, Z1 represents a delay element, and the delay is generated expressed by, xcex94t=T(i)xe2x88x92T(ixe2x88x921), and a datum received at the time of T(ixe2x88x921) is output in T(i).
When the equation (5) is substituted into the equation (4), the following equation is obtained.
Y(Z)=axc2x7b/(1xe2x88x92bxc2x7Zxe2x88x921)xe2x80x83xe2x80x83(6)
where, a=Axc2x7xcex94t, b=1/(1+Axc2x7xcex94t).
The frequency response characteristic extended on the Z plane shown in FIG. 6 is obtained by setting the maximum sampling intervals as 0.1 sec. The frequency response characteristic in a frequency range less than 10 Hz obtained when xcex94t is set at 0.01 sec is coincides with the characteristic shown by the equation (3).
It was confirmed that a uniform characteristic is obtained in a frequency range less than 4 Hz, even if xcex94t fluctuates.
It is to be understood that, although a peak is observed at a frequency of 5 Hz and at xcex94t=0.1 sec, it does not cause any problem because the significant frequency range is less than a half of the sampling frequency as decided by the sampling theory.